Formal Semantics for VHDL (The Springer International Series in Engineering and Computer Science #307)
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If different tools and users are to generate and read the same language then it is necessary that the same semantics is assigned by them to all constructs and elements of the language. The current IEEE standard VHDL language reference manual (LRM) tries to define VHDL as well as possible in a descriptive way, explaining the semantics in English. But rigor and clarity are very hard to maintain in a semantics defined in this way, and that has already given rise to many misconceptions and contradictory interpretations.
Formal Semantics for VHDL is the first book that puts forward a cohesive set of semantics for the VHDL language. The chapters describe several semantics each based on a different underlying formalism: two of them use Petri nets as target language, and two of them higher order logic. Two use functional concepts, and finally another uses the concept of evolving algebras.
Formal Semantics for VHDL is essential reading for researchers in formal methods and can be used as a text for an advanced course on the subject.
Details
- Publisher
- Springer US
- Format
- Paperback
- Published
- Sep 27, 2012
- ISBN-13
- 9781461359418
- Pages
- 249
- Printing
- Printed on demand
Formal Semantics for VHDL (The Springer International Series in Engineering and Computer Science #307) for groups: pricing
Volume pricing applies automatically in your cart. No codes, no account needed.
| Copies | Price per copy | You save |
|---|---|---|
| 25 – 49 | $96.79 | 12% off list |
| 50 – 99 | $95.69 | 13% off list |
| 100+ | $94.59 | 14% off list |
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