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System-on-a-Chip Verification: Methodology and Techniques book cover by Prakash Rashinkar, Peter Paterson, Leena Singh
Paperback

System-on-a-Chip Verification: Methodology and Techniques

by Prakash Rashinkar, Peter Paterson and Leena Singh

From $157.52 / copy at 25+ copies; lower per-copy prices at higher quantities (see Volume pricing) As low as $153.94 at 100+

Total $3,938.00

Paperback · 372 pages Springer US · 2013

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Paperback
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About the book

System-on-a-Chip Verification

System-On-a-Chip Verification: Methodology and Techniques is the first book to cover verification strategies and methodologies for SOC verification from system level verification to the design sign- off. The topics covered include Introduction to the SOC design and verification aspects, System level verification in brief, Block level verification, Analog/mixed signal simulation, Simulation, HW/SW Co-verification, Static netlist verification, Physical verification, and Design sign-off in brief. All the verification aspects are illustrated with a single reference design for Bluetooth application.
System-On-a-Chip Verification: Methodology and Techniques takes a systematic approach that covers the following aspects of verification strategy in each chapter:
  1. Explanation of the objective involved in performing verification after a given design step;
  2. Features of options available;
  3. When to use a particular option;
  4. How to select an option; and
  5. Limitations of the option.
This exciting new book will be of interest to all designers and test professionals.

Details

Publisher
Springer US
Authors
Prakash Rashinkar, Peter Paterson, Leena Singh
Format
Paperback
Published
Apr 23, 2013
ISBN-13
9781475774689
Pages
372
Printing
Printed on demand
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50 – 99 $155.73 13% off list
100+ $153.94 14% off list
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