Formal Semantics and Proof Techniques for Optimizing VHDL Models
by Kothanda Umamageswaran, Sheetanshu L. Pandey and Philip A. Wilsey
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Formal Semantics and Proof Techniques for Optimizing VHDL Models is written for hardware designers who are interested in the formal semantics of VHDL.
Details
- Publisher
- Springer US
- Authors
- Kothanda Umamageswaran, Sheetanshu L. Pandey, Philip A. Wilsey
- Format
- Paperback
- Published
- Oct 26, 2012
- ISBN-13
- 9781461373315
- Pages
- 158
- Printing
- Printed on demand
Formal Semantics and Proof Techniques for Optimizing VHDL Models for groups: pricing
Volume pricing applies automatically in your cart. No codes, no account needed.
| Copies | Price per copy | You save |
|---|---|---|
| 25 – 49 | $96.79 | 12% off list |
| 50 – 99 | $95.69 | 13% off list |
| 100+ | $94.59 | 14% off list |
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